1. Field of the Invention
The present invention relates to a digital serial interface circuit, more particularly relates to a serial interface circuit connected to a storage apparatus such as an HDD (hard disk drive), DVD (digital versatile disk)-ROM, CD (compact disk)-ROM, and tape streamer, and to a signal processing method of the same.
2. Description of the Related Art
In recent years, as an interface for transfer of multi-media data, the IEEE (The Institute of Electrical and Electronic Engineers) 1394 high performance serial bus for realizing high speed data transfer and real time transfer has become the standard.
In the data transfer by this IEEE 1394 serial interface, the transfer operation carried out in a network is referred to as a xe2x80x9csub-actionxe2x80x9d. Two sub-actions are prescribed.
One is an asynchronous transfer mode for making conventional requests, requesting acknowledgment, and confirming reception, while the other is an isochronous transfer mode in which the data is always sent from a certain node one time in 125 xcexcs.
In this way, the data at an IEEE 1394 serial interface having the two transfer modes is transferred in units of packets. In the IEEE 1394 standard, however, the smallest unit of data which is handled is a quadlet (=4 bytes=32 bits).
In the IEEE 1394 standard, usually the computer data is transferred by using the asynchronous transfer mode as shown in FIGS. 5A and 5B.
The asynchronous transfer mode, as shown in FIG. 5A, includes three transition states, that is, arbitration (arb) for securing the bus, packet transmission for transferring the data, and acknowledgment (ack).
The packet transmission is executed by the format as shown in FIG. 5B.
A first quadlet of the transfer packet is comprised of a destination ID region of 16 bits, a transaction label (t1) region of 6 bits, a retry code (rt) region of 2 bits, a transaction code (tcode) region of 4 bits, and a priority (pri) region of 4 bits.
The destination ID region indicates a bus no. and a node no. of this node, while the priority region indicates a priority level.
A second quadlet and a third quadlet are comprised by a source ID region of 16 bits and a destination offset region of 48 bits.
The source ID region indicates the node ID which sent the packet, while the destination offset region is comprised by a region of continuous highs and lows and indicates an address of an address space of the destination node.
A fourth quadlet is comprised by a data length region of 16 bits and an extended transaction code (extended tcode) region of 16 bits.
The data length region indicates the number of bytes of the received packet, while the extended tcode region is a region indicating an actual lock action carried out by the data of this packet where the tcode indicates a lock transaction.
A header CRC region added to the quadlet before the data field region is an error detection code of the packet header.
Further, the data CRC region added to the quadlet after the data region (data field) is the error detection code of the data field.
Further, FIG. 6 is a view of an example of the basic configuration of an isochronous communications packet.
As shown in FIG. 6, in an isochronous communications packet, the first quadlet is the 1394 header, the second quadlet is a header CRC (Header-CRC), the third quadlet is a CIP header 1 (CIP-Header 1), the fourth quadlet is a CIP header 2 (CIP-Header 2), the fifth quadlet is a source packet header (SPH), and the sixth and subsequent quadlets are data regions. The last quadlet is a data CRC (Data-CRC) region.
The 1394 header is comprised of a data length region representing the data length, a channel region indicating the no. of the channel to be transferred by this packet (any of 0 to 63), a tcode region representing the code of processing, and a synchronous code sy prescribed by each application.
The header CRC is the error detection code of the packet header.
The CIP-Header 1 is comprised of an SID (source node ID) region for the transmission node no., a DBS (data block size) region for the length of the data block, an FN (fraction number) region for the fraction number of the data in the formation of packets, a QPC (quadlet padding count) region for the number of quadlets of padding data, an SPH region for a flag indicating the existence/nonexistence of a source packet header, and a DBC (data block continuity counter) region for the counter detecting the number of isochronous packets.
Note that the DBS region represents the number of quadlets transferred by one isochronous packet.
The CIP-Header 2 is comprised of an FMT region for the signal format indicating the type of the data to be transferred and an FDF (format dependent field) region utilized corresponding to the signal format.
The SPH header has a time stamp region in which a value obtained by adding a fixed delay value to an axis at which the transport stream packet arrives is set.
Further, the Data-CRC is the error detection code of the data field.
As explained above, in the usual transfer of computer data carried out in the asynchronous transfer mode, SBP-2 (Serial Bus Protocol-2) is used as the protocol.
According to this protocol, when data is transferred from a storage device, that is, a target, to a host computer, that is, an initiator, the transfer is carried out by writing the data from the storage device to a memory of the host computer. When data is transferred from the host computer to the target, the transfer is carried out by the storage device reading the data of the memory of the host computer.
However, no processing circuit system has yet been established for controlling a so-called xe2x80x9ctransaction layerxe2x80x9d for converting the large volume of data to be stored in the storage device or read from the storage device into packets of the IEEE 1394 standard for transmission and reception.
Further, in a circuit system for realizing the asynchronous transfer and isochronous transfer mode, it is also necessary to configure the system so as to perform smooth reception processing in accordance with content of the data.
An object of the present invention is to provide a serial interface circuit capable of converting a large volume of data into packets based on a predetermined standard for transmission and reception and of performing smooth transmission and reception processing and a signal processing method of the same.
To attain the above object, according to a first aspect of the present invention, there is provided a serial interface circuit, for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, having a data processing circuit for adding a self-designating label to the data read out to its own node to generate a transmission packet and transmitting the same to the serial interface bus.
Preferably, the serial interface circuit has a control circuit for receiving a control packet from another node and starting up the data processing circuit when the content of the control packet indicates a request for transfer of data from its own node to the another node.
Further, the serial interface circuit has a demultiplexing circuit for receiving a packet transferred from another node through the serial interface bus, outputting the same to the control circuit when the received packet is a control packet, and outputting the same to the data processing circuit when the received packet is a response packet with respect to a transmission packet.
According to a second aspect of the present invention, there is provided a serial interface circuit, for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, having a data processing circuit which, when transferring the data of the another node to its own node, generates a request packet to which it has added a self-designating label, transmits the same to the serial interface bus, receives a response packet with respect to this request packet from the another node, takes out a data portion from the response packet, and transfers the same.
Preferably, the serial interface circuit has a control circuit for receiving a control packet from another node and starting up the data processing circuit when the content of the control packet indicates a request for transfer of data of the another node to its own node.
Further, the serial interface circuit has a demultiplexing circuit for receiving a packet transferred from another node through the serial interface bus, outputting the same to the control circuit when the received packet is a control packet, and outputting the same to the data processing circuit when the received packet is a response packet with respect to a transmission packet.
According to a third aspect of the present invention, there is provided a serial interface circuit, for performing transmission and reception of an asynchronous packet and an isochronous packet between its own node and another node connected to its own node via a serial interface bus, having a data processing circuit for adding a self-designating label to read data to generate a transmission packet and transmitting the same to the serial interface bus; a control circuit for receiving a control packet from the another node and starting up the data processing circuit when the content of the control packet indicates a request for transfer of data from its own node to the another node; and a demultlplexing circuit for receiving a packet transferred from the another node through the serial interface bus, outputting the same to the control circuit when the received packet is a control packet, outputting the same to the data processing circuit when the received packet is a response packet with respect to a transmission packet, and outputting the same to the application side when the received packet is isochronous stream packet data.
Preferably, the demultiplexing circuit discriminates a response packet based on the label and outputs the stream packet data to the corresponding different application sides for every channel.
According to a fourth aspect of the present invention, there is provided a serial interface circuit, for performing transmission and reception of an asynchronous packet and an isochronous packet between its own node and another node connected to its own node via a serial interface bus, having a data processing circuit which, when transferring data of the another node to its own node, generates a request packet to which it has added a self-designating label and transmits the same to the serial interface bus, receives a response packet with respect to this request packet from the another node, takes out the data portion from the response packet, and transfers the same; a control circuit for receiving a control packet from the another node and starting up the data processing circuit when the content of the control packet indicates a request for transfer of data of the another node to its own node; and a demultiplexing circuit for receiving a packet transferred from the another node through the serial interface bus, outputting the same to the control circuit when the received packet is the control packet, outputting the same to the data processing circuit when the received packet is a response packet with respect to a transmission packet, and outputting the same to the application side when the received packet is isochronous stream packet data.
Preferably, the demultiplexing circuit discriminates a response packet based on the label added to the response packet and the predetermined response code and outputs the stream packet data to the corresponding different application sides for every channel.
According to a fifth aspect of the present invention, there is provided a serial interface circuit, for performing transmission and reception of a packet, to which supply destination information has been added, between its own node and another node connected to its own node via a serial interface bus, having a demultiplexing circuit for demultiplexing a received packet based on the supply destination information of the received packet and outputting the same to the corresponding supply destination.
Preferably, the received packet is an asynchronous packet, and the supply destination information is a transaction label and transaction code information.
Alternatively, the received packet is an isochronous packet, and the supply destination information is a transaction code and channel information.
According to a sixth aspect of the present invention, there is provided a signal processing method of a serial interface circuit for performing transmission and reception of an asynchronous packet between its own node and another node connected to its own node via a serial interface bus, comprising, when transferring data of the another node to its own node, the steps of generating a request packet to which it has added a self-designating label, transmitting the same to the serial interface bus, receiving a response packet with respect to this request packet from the another node, and taking out the data portion from the response packet.
Preferably, when receiving a response packet, the data reception packet with respect to its own node is taken out based on the label added to the response packet and a predetermined response code.
According to the circuit of the present invention, in the case of for example a request from its own node to an another node for transfer of data of the storage device to the another node, the data of the storage device is read out by the data processing circuit. Then, a self-designating label is added to the read data which is then transmitted as a transmission asynchronous packet to the serial interface bus.
Further, in the present invention, the data processing circuit is started when the control circuit receives a control packet indicating a request for transfer of data from its own node to the another node.
Further, the demultiplexing circuit receives a packet transferred from the another node through the serial interface bus. When the received packet is a control packet, it is output to the control circuit, while when it is a response packet with respect to a transmission packet, it is output to the data processing circuit.
Further, according to the circuit of the present invention, when transferring data of the another node to its own node, the data processing circuit generates a request packet to which it has added a self-designating label and transmits the same to the serial interface bus.
Further, when a response packet with respect to this request packet is received from the another node, the data portion is taken out of the response packet and transferred to for example the storage device.
Further, according to the circuit of the present invention as applied to not only asynchronous communication, but also isochronous communication, the demultiplexing circuit receives the packet transferred from the another node through the serial interface bus.
When the received packet is a control packet, it is output to the control circuit, when the received packet is a response packet with respect to a transmission packet, it is output to the data processing circuit, while when the received packet is isochronous stream packet data, it is output to the application side.
Further, the demultiplexing circuit discriminates a response packet based on the label added to the response packet and a predetermined response code and outputs stream packet data to the corresponding different application sides for every channel.
Further, according to the circuit of the present invention, the demultiplexing circuit discriminates the destination of supply of the received packet based on the supply destination information of the received packet and outputs it to the corresponding supply destination.
For example, when the received packet is an asynchronous packet, it discriminates the supply destination based on a transaction label and transaction code information.
Further, when the received packet is an isochronous packet, it discriminates the destination of supply based on the transaction label and channel information.
According to the method of the present invention, when transferring data of the another node to its own node, a request packet to which it has added a self-designating label is generated and transmitted to the serial interface bus. Then, when a response packet with respect to this request packet is received from the another node, the data reception packet with respect to its own node is taken out based oh the label added to the response packet and a predetermined response code, and the data portion is taken out of the response packet.